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M61533FP
4ch Electronic Volume with AGC
REJ03F0059-0100Z Rev.1.0 Sep.19.2003
Features
Function Electric Volume Feature
* 0 to -87dB, -/1dBstep * 4ch SL/SR/C/SW independent Electric Volume * Controlled by trim volume data + master volume data.
Vc=1.8Vrms Can be set externally 0, +6, +9, +12dB 4step Controlled by serial data from microcomputer
AGC LPF Output Gain Control MUC I/F
Application
Mini Stereo etc.
Recommended Operating Condition
Supply Voltage Range VCC= 8 to 10V Typ:VCC=9V
System Block Diagram
SLIN SRIN
SLch volume SRch volume Cch volume SWch volume
SLOUT SROUT COUT AGC
0,+6, +9,+12dB
CIN SWIN
SW-LPF
SWOUT
Rev.1.0, Sep.19.2003, page 1 of 12
M61533FP
Block Diagram and Pin Configuration (Top view)
SLIN
1
LPF amp
20
SWLPF2
N.C.
2
SLch Volume
19
N.C.
N.C.
3
0 to -87dB,-
40k
18
SWOUT
SRIN
4
40k
SRch Volume
0 to -87dB,-
VREF amp
17
REFIN
CIN
5
40k
Cch Volume
0 to -87dB,-
16
REFOUT
SWIN
6
SWch Volume
0 to -87dB,-
15
SLOUT
VCC
7
40k
14
SROUT
DATA
8
MCU I/F
13
COUT
CLOCK
9
AGC SW Output Gain Control
12
SWLPF1
GND
10
0,+6,+9,+12dB
11
AGC
Rev.1.0, Sep.19.2003, page 2 of 12
M61533FP
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name SLIN N.C. N.C. SRIN CIN SWIN VCC DATA CLOCK GND AGC SWLPF1 COUT SROUT SLOUT REFOUT REFIN SWOUT N.C. SWLPF2 Function SLch volume input pin N.C. N.C. SRch volume input pin Cch volume input pin SWch volume input pin Power supply (Typ:9V) Input pin of Control data Input pin of Control clock Ground Attack/Recovery time control pin (by capacitor) SWch LPF (connected with resistance and capacitor) Cch output pin SRch output pin SLch output pin Vref output pin Vref input pin SWch output pin N.C. SWch LPF (connected with resistance and capacitor)
Absolute Maximum Ratings
Parameter Power Supply Power dissipation Thermal derating Operating temperature Storage temperature Symbol Vcc Pd K Topr Tstg Ratings 10.5 648 6.48 -20 to 75 -40 to 125 Unit V mW mW/C C C Ta 25C Ta > 25C Condition
Rev.1.0, Sep.19.2003, page 3 of 12
M61533FP
THERMAL DERATINGS (MAXIMUM RATING)
1.2
POWER DISSIPATION pd (W)
1.0
0.8
0.6
0.4
0.2
0 -40 0 40
75 80
120
150
AMBIENT TEMPERATURE Ta ( C)
Recommended Conditions
(Ta=25C, Unless otherwise noted)
Limits Parameter Power supply Logic "H" level input voltage Logic "L" level input voltage Symbol Vcc VIH VIL Min. 8 2.2 0 Typ. 9 Max. 10 5.5 0.6 Unit V V V Conditions VCC=9V GND reference VCC=9V GND reference
Rev.1.0, Sep.19.2003, page 4 of 12
M61533FP
Relationship Between Data and Clock
When DATA is "H", latch signal is created at the falling edge of CLOCK.
CLOCK D0 D1 D2 D3 D13 D14 D15
DATA
Data signal is read at the rising edge of CLOCK.
Make "H" at the timing which DATA of D0-D15 make latch.
Clock and Data Timings
(D0 D15) LATCH
tcr
CLOCK
tSLD 75% 25%
DATA
tHLD tSHD tHHD
tSLD
tHLD
tr tWHC
tf tWLC
Rev.1.0, Sep.19.2003, page 5 of 12
M61533FP
Timing Definition of Digital Block
Limits Parameter CLOCK cycle time CLOCK pulse width("H" level) CLOCK pulse width ("L" level) Rising time of clock and data Falling time of clock and data DATA setup time (Rising time of clock) DATA setup time (Falling time of clock) DATA hold time("H" level) DATA hold time("L" level) Symbol tcr tWHC tWLC tr tf tSHD tSLD tHHD tHLD Min. 4 1.6 1.6 0.8 0.8 0.8 0.8 Typ. Max. 0.4 0.4 Unit s
Data Control Specification
Four types of input format can be selected by changing the D14/D15 slot setting status. (Initialize all data of the 4 formats when power supply(VCC) turn on.) Note : No guarantee except for these code. (1) D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14 D15 2
SLch Trim volume
2
SRch Trim volume 0 0 0 0 0 1 0 0
(2)
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14 D15 2
Cch Trim volume
2
SWch Trim volume 1
1
SWch Output gain control 0 0 0 0 1
(3)
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14 D15 3
SLch Master volume
3
SRch Master volume 0 0 0 0 1 0
(4)
D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14 D15 3
Cch Master volume
3
SWch Master volume 0 0 0 0 1 1
Rev.1.0, Sep.19.2003, page 6 of 12
M61533FP
Setting Code
It's initial setting when VCC turn on. 1 SWch Output gain control
D9b 0dB +6dB +9dB +12dB 0 0 1 1 D10b 0 1 0 1
2 SL/SR/C/SWch Trim volume
SLch SRch ATT Cch SWch 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB
D0a D1a D2a D3a D4a D5a D6a D7a D0b D1b D2b D3b D4b D5b D6b D7b
3 SL/SR/C/SWch Master volume
SLch SRch Cch SWch 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -48dB -52dB -56dB -60dB -64dB -68dB -72dB -76dB - dB
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d
ATT
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Note1: Volume ATT controlled by trim volume data + master volume data. Note2: When trim volume data + master volume data is under -87dB setting , volume ATT keep -87dB.
ex) When trim volume data:-15dB / master volume data -76dB setting , volume ATT keep -87dB.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Rev.1.0, Sep.19.2003, page 7 of 12
M61533FP
Electrical characteristics
Unless otherwise noted, Ta=25C, Vcc=9V, f=1kHz, Trim/Master Volume=0dB, Output Gain Control=0dB, SWch LPF fc=300Hz
Limits Parameter Power circuit current Input/output Maximum input voltage Maximum output voltage Symbol IACC VIM VOM1 VOM2 Pass gain Output noise voltage GV Vno1 Min. 1.4 1.6 -2 Typ. 15 1.8 2.0 0 1.3 Max. 30 2.0* +2 4.0 Unit mA Vrms Vrms Vrms dB Vrms Test conditions when no signal is provided (1,4,5,6)PIN input,(13,14,15,18)PIN output, RL=10k, THD=1% 6PIN input, 18PIN output, RL=10k, THD=5% , f=100Hz (1,4,5)PIN input , (13,14,15)output, RL=10k, THD=5% (1,4,5,6)PIN input, (13,14,15,18) output, Vi=0.5Vrms, FLAT JIS-A, when no signal is provided, (1,4,5)PIN Rg=0 , (13,14,15)PIN output SL/SR/Cch volume =0dB
Vno2
1.3 8.0
4.0 16
Vrms Vrms JIS-A, when no signal is provided, 6PIN Rg=0 , 18PIN output,
SL/SR/Cch volume =-dB SWch volume =0dB SWch volume =dB (1,4,5)PIN input, (13,14,15)output, BW:400 30kHz, Vo=0.5Vrms, RL=10k 6PIN input,12PIN output, 30kHz L.P.F, f=100Hz, Output Gain Control =0dB, Vi=0.5Vrms(AGC:off), RL=10k 6PIN input, 12PIN output, 30kHz L.P.F, f=100Hz, Output Gain Control =+12dB, Vi=0.7Vrms(AGC:on), RL=10k Vo=1Vrms, (12,13,14,15) PIN output, JIS-A, VOL=- 6PIN input, 12PIN output, f=100Hz, Vi=0.1Vrms, FLAT, Output Gain Control =+12dB (1,4,5,6)PIN input, (12,13,14,15)PIN output, Vi=0.5Vrms, JIS-A, RL=47k, Rg=0k 6PIN input, 12PIN output, RL=10k, Output Gain Control =+12dB 6PIN input, 12PIN output, RL=10k, Output Gain Control =+12dB
Distortion THD1 THD2
8.0 0.005 0.05
16 0.1 0.2
Vrms % %
THD3
5
%
Maximum attenuation Maximum gain
ATT GVM
+10
-92 +12
-87 +14
dB dB
Cross talk between channels AGC Attack time Recovery time
CT
-70
-55
dB
TAGCAT TAGCRE

40 850

ms ms
* Note : The signal can not be inputted to more than 2Vrms. Keep this limit.
Rev.1.0, Sep.19.2003, page 8 of 12
M61533FP
LPF
Equivalent circuit of LPF
C1
Vin
R1
R2
+K C2
Vout
F(s) =
Vout = Vin
1 K R1R2C1C2 2 S + R11 + R21 +( 1-K ) R21 C1 C2 C1
S+
1 R1R2C1C2
0
=
1 R1R2C1C2
Q=
1 R2C2 R1C2 R1C1 R1 C1 + R2 C1 + ( 1-K ) R2 C2
Frequency characteristics (SWch LPF)
R1=2.2k, R2=4.7k, C1=0.22F, C2= 0.1F, K=1 .. . Q = 0.68, fc =. 300Hz *This frequency response is a simulation result.
Rev.1.0, Sep.19.2003, page 9 of 12
M61533FP
AGC
*Note : Less than 2Vrms
SWch Output Gain Control
+26dB(total:0dB) to +38dB (total:+12dB)
SWIN
Max:2Vrms
SWch volume
-26dB
SWOUT
AGC out
AGC in
AGC comp
Attack time / Recovery time EX) C = 1.0 F Attack time 40 mS Recovery time 850 mS Attack / Recovery time is controlled by this capacitor.
1.0
AGC
AGC characteristics
Output Gain : 0dB
+10
+5.1dBV (1.8Vrms: TYP)
Output Gain : +6dB
+10
+5.1dBV (1.8Vrms: TYP)
AGCout (dBV)
AGCout (dBV)
0
10dB
0
10dB
+ 9.1dBV (2.85Vrms)
-10
+5.1dBV (1.8Vrms) +6dBV (2Vrms)
-10
-0.9dBV (0.90Vrms) +6dBV (2Vrms)
-20 -20 -10 0 +10
-20 -20 -10 0 +10
AGCin (dBV)
Output Gain : +9dB
+10
+5.1dBV (1.8Vrms: TYP)
AGCin (dBV)
Output Gain : +12dB
+10
+5.1dBV (1.8Vrms: TYP)
AGCout (dBV)
0
AGCout (dBV)
10dB
0
10dB +3.1dBV (1.43Vrms)
-10
-4dBV (0.63Vrms) +6dBV (2Vrms)
-10
-6.9dBV (0.45Vrms) +6dBV (2Vrms)
-20 -20 -10 0 +10
-20 -20 -10 0 +10
AGCin (dBV)
AGCin (dBV)
Rev.1.0, Sep.19.2003, page 10 of 12
M61533FP
Application Example
* Note : The signal can not be inputted to more than 2Vrms.
0.1 10
SLch IN
Max:2Vrms
1
N.C. LPF amp
20
4.7k
N.C.
2
N.C. SLch Volume
0 to -87dB,-
19
0.22
2.2k
SRch OUT
10
3
40k
18
10
SRch IN
Max:2Vrms
4
40k
10
SRch Volume
0 to -87dB,-
VREF amp
17
100
Cch IN
Max:2Vrms
5
40k
10
Cch Volume
0 to -87dB,-
16
100 10
SLch OUT
SWch IN
Max:2Vrms
6
SWch Volume
0 to -87dB,-
15
10
SRch OUT
VCC:9V
7
40k
14
10
Cch OUT
8
MCU MCU I/F
13
9
AGC SW Output Gain Control
0,+6,+9,+12dB
12
10
11
1
Rev.1.0, Sep.19.2003, page 11 of 12
M61533FP
Package Dimensions
Rev.1.0, Sep.19.2003, page 12 of 12
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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